The on-going demand for high performance electronic systems has driven the need for high-speed digital Very Large Scale Integration (VLSI) chips. VLSI implementations have proceeded along two inter-related directions: higher performance and higher density (more devices per unit area). While modern VLSI chips have achieved astonishingly high levels of performance and chip density there is a very strong demand for even higher levels.
One serious impediment to achieving what is demanded is power consumption. As a rule of thumb higher performance requires more power. But, more power produces more heat, which increases failure rates. Consequently, power consumption is the predominant challenge in improving modern high performance VLSI chips and systems.
Almost all modern VLSI designs are clocked. That is, the operations of the gates within a VLSI device are synchronized to act together by clock signals. So long as the gates can keep up, the higher the clock rate the faster the performance. Unfortunately, as clock rates and VLSI chip densities increase it becomes very difficult to ensure that all of the chips can keep up with the clocks. One reason for this is that each device in a VLSI chip needs its own clock signal, but not all sequential elements are the same distance from the clock signal source, which means that all clock lines are the not the same length. Different lengths coupled with unavoidable signal delays caused by distributed inductances and capacitances mean that clock signals arrive at different devices at different times (clock skew). Such can effectively limit the performance of a VLSI chip.
Compounding clocking problems is the fact that clocking requires power. In fact, the on-chip clock distribution network (CDN) of modern VLSI chips often consumes more than 35% of the total chip power and can occasionally require as much as 70%.
Various approaches have been used in the prior art to address the clocking problems. One approach to decreasing CDN power consumption is to use resonant clocks in the clock distribution network. FIG. 1 illustrates a resonant clock 10. Ideally, by oscillating clock energy between the electric field of capacitance Cs 12 and the magnetic field of inductor Ls 14 the clock energy is recycled and power consumption is decreased (ideally to zero). The resonant frequency of the tank circuit is ideally:f=1/2π√{square root over (LsCs)}
However, to provide the required CMOS logic levels of zero and Vdd 16a positive bias is obtained by adding a decoupling capacitor Cd 18 on the grounded end of the paralleled inductor Ls 14 as shown in FIG. 1. That additional capacitance Cd 18 creates a parasitic series LC tank circuit. Careful sizing of Cd 18 is required to ensure that the series resonant frequency is well separated from the parallel resonant frequency, i.e.:1/2π√{square root over (LsCd)}<<1/2π√{square root over (LsCs)}
In practice, pure series/parallel LC tanks are not seen because of unavoidable wire resistances, specifically: Rwl 20, the conductor resistance between the clock driver and the inductor, Rwr 22 the conductor resistance between the inductor 14 and the clock capacitor Cs 12 the driving element resistance Rdir 24 and the parasitic resistance of the inductor Rs 26
Those unavoidable wire resistances shift the resonance frequency of the parallel LC oscillator downward and change that oscillator's Q. Furthermore, the placement of an LC tank in the tree determines the attenuation. Different placements mean different attenuation. Consequently, where the LC tanks are placed in a clock distribution network is of utmost concern.
While very promising in theory, resonant clocks 10 are usually restricted to VLSI H-tree clock distribution networks 28 that use H-trees. Referring now to FIGS. 2a and 2b, an H-tree 30 is a conductor topology for minimizing clock skew by making interconnections to VLSI circuit “subunits” equal in length by using a regular pattern of clock line conductors 34. An H-tree 30 is a symmetric tree structure and has been used in the top-level tree topology to drive clock grids in high performance IC designs.
In the prior art are several techniques of using resonate H-trees 30 to drive clock grids and to obtain the correct LC placement and sizing. When H-tree clock distribution networks 28 incorporate resonant tanks the LC tanks are inserted at points in the H-tree clock distribution networks 28 so as to resonate each subunit clock sector. Refer to FIG. 2b for a depiction of a resonant H-tree grid 38 augmented by distributed LC tanks. While an H-tree 30 can have many different levels, in the prior art the LC tanks were always placed at the input of the second level in a 2-level H-tree network.
While conceptually interesting, H-trees 30 in general and H-tree clock distribution networks 28 in particular are seldom if ever used. A major problem is that H-trees 30 require an even (balanced) distribution of gates, terminals, loads, distributed capacitance and inductances and conductors. Such limitations are neither practical nor realistic in actual VLSI H-tree clock distribution network 28 designs.
One issue not well-addressed in the prior art is the uneven loading of clock distributions. The distribution of sink loads significantly alters resonant behavior and prevents correct functionality of LC tanks. Resonant trees present several unique challenges to automated designs compared to buffered trees. First, the parasitic resistances and inductances in a clock distribution alter the resonant frequency. Second, the resistances add attenuation at high frequencies. No successful prior art methods to address those problems have been proposed.
Therefore, a system and method that addresses and allows uneven loading of clock tree distributions would be beneficial. Even more useful would be a system and method that addresses uneven loading of the clock tree distributions while also enabling an increase in power efficiency. Ideally, the method would be suitable for automatic implementation at the design level.